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2016
"CloudRadar: A Real-time Side-channel Attack Detection System in Clouds",
Research in Attacks, Intrusion and Defense, September 2016.
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"Monitoring and Attestation of Virtual Machine Security Health in Cloud Computing",
IEEE Micro Special Issues on Security, vol. 36, issue 5, Sept/Oct 2016.
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"Newcache: secure cache architecture thwarting cache side channel attacks",
IEEE Micro Special Issues on Security, vol. 36, issue 5, Sept/Oct 2016.
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"CATalyst: Defeating Last-Level Cache Side Channel Attacks in Cloud Computing",
Proceedings of IEEE Symposium on High Performance Computer Architecture (HPCA'16), Barcelona, Spain, March 2016.
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"Implicit Sensor-based Authentication of Smartphone Users with Smartwatch",
Proceedings of the Workshop on Hardware and Architectural Support for Security and Privacy (HASP), June 2016.
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"Cloud Server Benchmark Suite for Evaluating New Hardware Architectures",
IEEE Computer Architecture Letters, July-Dec 2016.
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"A Hardware-based Technique for Efficient Implicit Information Flow Tracking",
IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Austin, IEEE, 07/11/2016.
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"Using Moving Target Defense for Secure Hardware Design",
Princeton University Department of Electrical Engineering Technical Report CE-L2016-002, 2016 .
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2015
"A 32kB Secure Cache Memory with Dynamic Replacement Mapping in 65nm bulk CMOS",
IEEE Asian Solid-States Circuit Conference (A-SSCC), Xiamen, China, November 2015.
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"Disruptive Prefetching: Impact on Side-Channel Attacks and Cache Designs",
Proceedings of the 8th ACM International Systems and Storage Conference, Haifa, Israel, May 2015.
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"Last-Level Cache Side-Channel Attacks are Practical",
Proceedings of IEEE Symposium on Security and Privacy, San Jose, pp. 605-622, May 2015.
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"CloudMonatt: an Architecture for Security Health Monitoring and Attestation of Virtual Machines in Cloud Computing",
Proceedings of The 42nd International Symposium on Computer Architecture, Portland, pp. 362-274, June 2015.
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"Can randomized mapping secure instruction caches from side-channel attacks?",
in Proceedings of the Workshop on Hardware and Architectural Support for Security and Privacy (HASP), Portland, June 13, 2015.
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"Multi-sensor authentication to improve smartphone security",
Proceedings of International Conference on Information Systems Security and Privacy, February 2015.
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"Implicit Authentication for Smartphone Security",
Information Systems Security and Privacy, vol. 576: Springer, pp. 160-176, 2015 .
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"Mapping the Intel Last-Level Cache",
IACR Cryptology ePrint Archive, Report 2015/905, 2015 .
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"Performance Measurement and Security Testing of a Secure Cache Design",
MSE Thesis, Electrical Engineering Department, Princeton, Princeton University, 2015 .
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2014
"Cyber Defenses for Physical Attacks and Insider Threats in Cloud",
Proceedings of the ACM Symposium on Information, Computer and Communications Security (AsiaCCS), June 2014.
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"Random Fill Cache Architecture",
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture (Micro-47), Cambridge, pp. 203-215, December 2014.
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"Hardware-Enhanced Security for Cloud",
Secure Cloud Computing , Berlin, Springer, pp. 57-76, 2014 .
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"New Models of Cache Architectures Characterizing Information Leakage from Cache Side",
Proceedings of Annual Computer Security Applications Conference (ACSAC), December 2014, pp. 96-105, 2014 .
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2013
"BitDeposit: Deterring Attacks and Abuses of Cloud Computing Services Through Economic Measures",
in Proceedings of the Workshop on Assured Cloud Computing (ACC), May 2013.
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"Characterizing Hypervisor Vulnerabilities in Cloud Computing Servers",
in Proceedings of the Workshop on Security in Cloud Computing (SCC), May 2013.
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"Security Testing of a Secure Cache Design",
in Proceedings of the Workshop on Hardware and Architectural Support for Security and Privacy (HASP), June 24, 2013.
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"Side Channel Vulnerability Metrics: the Promise and the Pitfalls",
in Proceedings of the Workshop on Hardware and Architectural Support for Security and Privacy (HASP), June 24, 2013.
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