- Home
- People
- Projects
- Practical Security Verification
- Secure Cloud Computing
- Security of AI Systems
- Deep Learning for Security
- Smartphone Security
- Cache Side-Channels and Secure Caches
- De-anonymization
- Running Unvetted Programs
- Secure RISC-V processor
- SP and Bastion Secure Processor Architectures
- Crypto Acceleration
- OpenSPARC Researh
- SecureCore
- Advanced Bit Manipulation
- PAX
- PLX
- Publications
- Research
- Conference and Journals
- Project Archive
- Photos
Performance Measurement and Security Testing of a Secure Cache Design
Source:
MSE Thesis, Electrical Engineering Department, Princeton University, Princeton (2015)| Attachment | Size |
|---|---|
| haow-mse-thesis.pdf | 1.55 MB |