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Journal Article
"Making Security Validation as Easy as Performance Evaluation",
Princeton University Department of Electrical Engineering Technical Report CE-L2009-005, November 2009.
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"SP Reference Manual Addendum -- Secure Stacks for TSMs and Emulation of SP Interrupt Protection",
Princeton University Department of Electrical Engineering Technical Report CE-L2009-006, August 2009.
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"Alternative application-specific processor architectures for fast arbitrary bit permutations",
International Journal of Embedded Systems, vol. 3, issue 4, pp. 219-228, 2008 .
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"Fast Bit Gather, Bit Scatter and Bit Permutation Instructions for Commodity Microprocessors",
Journal of Signal Processing Systems, vol. 53, issue 1-2: Springer New York, pp. 145-169, 11/2008.
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"Framework for Design Validation of Security Architectures",
Princeton University Department of Electrical Engineering Technical Report CE-L2008-013, November 2008.
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"Stability and Benefits of Suboptimal Utility Maximization",
submitted to IEEE Transactions on Networking, Nov. 4.
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"SecureCore Prototype/Demo Manual",
Princeton University Department of Electrical Engineering Technical Report CE-L2008-009, August 2008.
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"SP Processor Architecture Reference Manual",
Princeton University Department of Electrical Engineering Technical Report CE-L2008-008, August 2008.
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"SP-PAX: Hardware implementation of SP module with PAX cryptoprocessor",
Princeton University Department of Electrical Engineering Technical Report CE-L2008-006, April 2008.
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"Aiding Side-channel Attacks on Cryptographic Software with Satisfiability-based Analysis",
IEEE Transactions on VLSI, vol. 15, issue 4, pp. 465-470, April 2007.
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"Virtualization of a Processor-based Crypto-Protection Mechanism and Integration within a Separation Kernel Architecture",
Princeton University Department of Electrical Engineering Technical Report CE-L2006-006, November 2006.
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"PLX: An Instruction Set Architecture and Testbed for Multimedia Information Processing",
Journal of VLSI Signal Processing, vol. 40, issue 1, pp. 85-108, 2005 .
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"Single-Cycle Bit Permutations with MOMR Execution",
Journal of Computer Science and Technology, vol. 20, issue 5, pp. 577-585, September 2005.
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"Architectural Techniques for Accelerating Subword Permutations with Repetitions",
IEEE Transactions on Very Large Scale Integration Systems, vol. 11, issue 3, pp. 325-335, June 2003.
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"Efficient Permutation Instructions for Fast Software Cryptography",
IEEE Micro, vol. 21, issue 6, pp. 56-69, Dec. 2001.
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"Precision Architecture",
IEEE computer, vol. 22, issue 1, pp. 14, 01/1989.
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"Hewlett-Packard Precision Architecture: the Processor",
HP Journal, vol. 37, issue 8, pp. 19, 08/1986.
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Conference Paper
"Actionbert: leveraging user actions for semantic understanding of user interfaces",
AAAI Conference on Artificial Intelligence (AAAI), 2021 .
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"New models for understanding and reasoning about speculative execution attacks",
IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2021, 2021 .
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"Smartphone Impostor Detection with Behavioral Data Privacy and Minimalist Hardware Support",
TinyML Research Symposium, 2021 .
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"SoK: Hardware Defenses Against Speculative Execution Attacks",
IEEE International Symposium on Secure and Private Execution Environment Design, 2021 .
Abstract
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"Position Paper: Consider Hardware-enhanced Defenses for Rootkit Attacks",
Proceedings of the 9th International Workshop on Hardware and Architectural Support for Security and Privacy (HASP), 2020 .
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"Model Inversion Attacks Against Collaborative Inference",
ACM Annual Computer Security Applications Conference (ACSAC): ACM, 12/09/2019.
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"Power-Grid Controller Anomaly Detection with Enhanced Temporal Deep Learning",
IEEE International Conference on Trust, Security and Privacy in Computing and Communications (TrustCom), 05/08/2019.
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"Sensitive-sample Fingerprinting of Deep Neural Networks",
IEEE Conference on Computer Vision and Pattern Recognition (CVPR): IEEE, 15/06/2019.
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