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Hilewitz, Y., Shi, Z.J., Lee, R.B.,
"Comparing Fast Implementations of Bit Permutation Instructions",
Proceedings of the 38th Annual Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, USA, pp. 1856-1863, Nov. 2004.
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L
Lee, R.B., Yang, X., Shi, Z.J.,
"Single-Cycle Bit Permutations with MOMR Execution",
Journal of Computer Science and Technology, vol. 20, issue 5, pp. 577-585, September 2005.
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Lee, R.B., Yang, X., Shi, Z.J.,
"Validating Word-oriented Processors for Bit and Multi-Word Operations",
Proceedings of the Asia-Pacific Computer Systems Architecture Conference (ACSAC 2004), Beijing, China, pp. 473-488, Sept. 2004.
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Lee, R.B., Rivest, R.L., Robshaw, M.J.B., Shi, Z.J., Yin, Y.L.,
"On Permutation Operations in Cipher Design",
Proceedings of the International Conference on Information Technology (ITCC 2004), Las Vegas, Nevada, USA, pp. 569-577, April 5-7, 2004.
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Lee, R.B., Rivest, R.L., Robshaw, M.J.B., Shi, Z.J., Yin, Y.L.,
"Permutation Operations in Block Ciphers",
Book chapter in Nadia Nedjah and Luiza de Macedo Mourelle eds., Embedded Cryptographic Hardware: Design and Security, New York, Nova Science Publisher, ISBN: 1-59454-145-0, Chapter 13, pp. 219-236, 2004 .
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Lee, R.B., Karig, D., McGregor, J.P., Shi, Z.,
"Enlisting Hardware Architecture to Thwart Malicious Code Injection",
Proceedings of the International Conference on Security in Pervasive Computing (SPC-2003), Boppard, Germany, pp. 237-252, March 2003.
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Lee, R.B., Fiskiran, M., Shi, Z., Yang, X.,
"Refining Instruction Set Architecture for High-Performance Multimedia Processing in Constrained Environments",
Proceedings of the 13th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2002), San Jose, California, pp. 253-264, July 2002.
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Lee, R.B., Shi, Z., Yang, X.,
"How a Processor can Permute n bits in O(1) cycles",
Proceedings of IEEE Hot Chips 14 - A Symposium on High Performance Chips, Stanford University, USA, Aug. 2002.
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Lee, R.B., Shi, Z., Yang, X.,
"Efficient Permutation Instructions for Fast Software Cryptography",
IEEE Micro, vol. 21, issue 6, pp. 56-69, Dec. 2001.
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McGregor, J.P., Karig, D., Shi, Z., Lee, R.B.,
"A Processor Architecture Defense against Buffer Overflow Attacks",
Proceedings of the IEEE International Conference on Information Technology: Research and Education (ITRE 2003), Newark, New Jersey, USA, pp. 243-250, Aug. 2003.
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S
Shi, Z.J., Lee, R.B.,
"Implementation Complexity of Bit Permutation Instructions",
Proceedings of the 37th Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, Pacific Grove, California, USA, pp. 879-886, Nov. 2003.
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Shi, Z., Yang, X., Lee, R.B.,
"Arbitrary Bit Permutations in One or Two Cycles",
Proceedings of the 14th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2003), The Hague, The Netherlands, pp. 237-247, June 2003.
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Shi, Z., Lee, R.B.,
"Subword Sorting with Versatile Permutation Instructions",
Proceedings of the International Conference on Computer Design (ICCD 2002), Freiburg, Germany, pp. 234-241, Sept. 2002.
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Shi, Z., Lee, R.B.,
"Bit Permutation Instructions for Accelerating Software Cryptography",
Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2000), Boston, Massachusetts, USA, pp. 138-148, July 2000.
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Z
Shi, Z.J., Yang, X., Lee, R.B.,
"Alternative application-specific processor architectures for fast arbitrary bit permutations",
International Journal of Embedded Systems, vol. 3, issue 4, pp. 219-228, 2008 .
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