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"Stability and benefits of suboptimal utility maximization",
IEEE/ACM Transactions on Networking, vol. 19, issue 4, 2011 .
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"Scalable Architectural Support for Trusted Software",
The 16th IEEE International Symposium on High-Performance Computer Architecture (HPCA), Bangalore, India, Jan 9-14 2010.
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"Scalable Security Architecture for Trusted Software",
PhD Thesis, Electrical Engineering Department, Princeton, NJ, Princeton University, pp. 231, 2010 .
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"Securing the Use of Sensitive Data on Remote Devices Using a Hardware-Software Architecture",
PhD Thesis, Electrical Engineering Department, Princeton, NJ, Princeton University, pp. 294, 2010 .
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"Securing the Dissemination of Emergency Response Data with an Integrated Hardware-Software Architecture",
2nd International Conference on Trusted Computing (TRUST 2009), Oxford, U.K., pp. 133-156, April 2009.
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"SP Reference Manual Addendum -- Secure Stacks for TSMs and Emulation of SP Interrupt Protection",
Princeton University Department of Electrical Engineering Technical Report CE-L2009-006, August 2009.
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"Stability and Benefits of Suboptimal Utility Maximization",
submitted to IEEE Transactions on Networking, Nov. 4.
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"SecureCore Prototype/Demo Manual",
Princeton University Department of Electrical Engineering Technical Report CE-L2008-009, August 2008.
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"SP Processor Architecture Reference Manual",
Princeton University Department of Electrical Engineering Technical Report CE-L2008-008, August 2008.
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"SP-PAX: Hardware implementation of SP module with PAX cryptoprocessor",
Princeton University Department of Electrical Engineering Technical Report CE-L2008-006, April 2008.
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"Secure Key Management Architecture Against Sensor-node Fabrication Attacks",
IEEE GlobeCom 2007, Washington, DC, November 2007.
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SP Processor Architecture Reference Manual,
, Princeton University Department of Electrical Engineering Technical Report CE-L2007-009, 11/21/2007.
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"Scope of DDoS Countermeasures: Taxonomy of Proposed Solutions and Design Goals for Real-World Deployment",
8th International Symposium on Systems and Information Security (SSI'2006), November 2006.
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"Satisfiability-based Framework for Enabling Side-channel Attacks on Cryptographic Software",
Proceedings of the Conference on Design, Automation and Test in Europe (DATE 2006), Munich, Germany, pp. 18-23, March 2006.
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"Single-Cycle Bit Permutations with MOMR Execution",
Journal of Computer Science and Technology, vol. 20, issue 5, pp. 577-585, September 2005.
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"Security as a New Dimension in Embedded System Design",
Proceedings of the 41st Design Automation Conference (DAC 2004), San Diego, California, USA, pp. 753-760, June 2004.
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"Scoping Security Issues for Interactive Grids",
Proceedings of the 37th Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, USA, pp. 367-373, Nov. 2003.
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"Subword Sorting with Versatile Permutation Instructions",
Proceedings of the International Conference on Computer Design (ICCD 2002), Freiburg, Germany, pp. 234-241, Sept. 2002.
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"Securing Wireless Data: System Architecture Challenges",
Proceedings of the 15th IEEE International Symposium on System Synthesis (ISSS 2002), Kyoto, Japan, pp. 195-200, Oct. 2002.
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"System Design Methodologies for a Wireless Security Processing Platform",
Proceedings of the 39th ACM/IEEE Design Automation Conference (DAC 2002), New Orleans, Louisiana, USA, pp. 777-782, June 2002.
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"Subword Permutation Instructions for Two-Dimensional Multimedia Processing in MicroSIMD Architectures",
Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2000), Boston, Massachusetts, USA, pp. 3-14, July 2000.
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"Trust but Verify: Trust Evidence for Hypervisor-Secure Virtualization",
Princeton University Department of Electrical Engineering Technical Report CE-L2011-008, Nov. 16, 2011.
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"Tuning Instruction Customisation for Reconfigurable System-on-Chip",
Proceedings of the 22nd IEEE International SOC Conference, Sept. 9-11, 2009.
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"The Reduced Address Space for Application Memory Authentication",
Proceedings of the 11th Information Security Conference (ISC'08), September 2008.
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"TEC-Tree: A Low Cost, Parallelizable Tree for Efficient Defense against Memory Replay Attacks",
Proc. Workshop on Cryptographic Hardware and Embedded Systems (CHES 2007), Vienna, Austria, pp. 289-302, September 2007.
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