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H
Achieving Very Fast Bit Matrix Multiplication in Commodity Microprocessors,
, Princeton University Department of Electrical Engineering Technical Report CE-L2007-006, August 2007.
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"Fast Bit Compression and Expansion with Parallel Extract and Parallel Deposit Instructions",
Proceedings of the IEEE 17th International Conference on Application-Specific Systems, Architectures and Processors (ASAP), pp. 65-72, 11/09/2006.
Abstract
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"Comparing Fast Implementations of Bit Permutation Instructions",
Proceedings of the 38th Annual Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, USA, pp. 1856-1863, Nov. 2004.
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"A Hardware-based Technique for Efficient Implicit Information Flow Tracking",
IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Austin, IEEE, 07/11/2016.
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"Cyber Defenses for Physical Attacks and Insider Threats in Cloud",
Proceedings of the ACM Symposium on Information, Computer and Communications Security (AsiaCCS), June 2014.
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"Hardware-Enhanced Security for Cloud",
Secure Cloud Computing , Berlin, Springer, pp. 57-76, 2014 .
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"BitDeposit: Deterring Attacks and Abuses of Cloud Computing Services Through Economic Measures",
in Proceedings of the Workshop on Assured Cloud Computing (ACC), May 2013.
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"Architectural Support for Hypervisor-Secure Virtualization",
in Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 3–7, 2012.
Abstract
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"Physical Attack Protection with Human-Secure Virtualization in Data Centers",
Workshop on Open Resilient human-aware Cyber-physical Systems (WORCS), June 25, 2012.
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"Rapid Single-Chip Secure Processor Prototyping on OpenSPARC FPGA Platform",
in Proceedings of the Rapid System Prototyping Symposium (RSP), May 24-27, 2011.
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"A Case for Hardware Protection of Guest VMs from Compromised Hypervisors in Cloud Computing",
in Proceedings of the Second International Workshop on Security and Privacy in Cloud Computing (SPCC), June 20-24, 2011.
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"Eliminating the Hypervisor Attack Surface for a More Secure Cloud",
in Proceedings of the Conference on Computer and Communications Security (CCS), Oct. 17-21, 2011.
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"Trust but Verify: Trust Evidence for Hypervisor-Secure Virtualization",
Princeton University Department of Electrical Engineering Technical Report CE-L2011-008, Nov. 16, 2011.
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"General-purpose FPGA Platform for Efficient Encryption and Hashing",
in Proceedings of the Application-specific Systems, Architectures and Processors conference, ASAP, July 7-9, 2010.
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"A Framework for Testing Hardware-Software Security Architectures",
Annual Computer Security Applications Conference, Austin, Texas USA, December 6 2010.
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"Evaluation of OpenSPARC FPGA Platform as a Security and Performance Research Platform",
Princeton University Department of Electrical Engineering Technical Report CE-L2010-002, Sept. 6, 2010.
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"A Framework for Testing Hardware-Software Security Architectures",
Princeton University Department of Electrical Engineering Technical Report CE-L2009-001, February 2009.
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"SP Reference Manual Addendum -- Secure Stacks for TSMs and Emulation of SP Interrupt Protection",
Princeton University Department of Electrical Engineering Technical Report CE-L2009-006, August 2009.
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"Framework for Design Validation of Security Architectures",
Princeton University Department of Electrical Engineering Technical Report CE-L2008-013, November 2008.
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"SecureCore Prototype/Demo Manual",
Princeton University Department of Electrical Engineering Technical Report CE-L2008-009, August 2008.
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"SP Processor Architecture Reference Manual",
Princeton University Department of Electrical Engineering Technical Report CE-L2008-008, August 2008.
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Authority SP_CCS2007,
, 2007 .
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K
"Security as a New Dimension in Embedded System Design",
Proceedings of the 41st Design Automation Conference (DAC 2004), San Diego, California, USA, pp. 753-760, June 2004.
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Decimation Tools Set,
, Princeton University Department of Electrical Engineering Technical Report CE-L2007-014, November 2007.
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PAX: A Cryptographic Processor with Parallel Table Lookup and Wordsize Scalability,
, Princeton University Department of Electrical Engineering Technical Report CE-L2007-010, November 2007.
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