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A
"Architectural Techniques for Accelerating Subword Permutations with Repetitions",
IEEE Transactions on Very Large Scale Integration Systems, vol. 11, issue 3, pp. 325-335, June 2003.
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"Arbitrary Bit Permutations in One or Two Cycles",
Proceedings of the 14th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2003), The Hague, The Netherlands, pp. 237-247, June 2003.
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"A Processor Architecture Defense against Buffer Overflow Attacks",
Proceedings of the IEEE International Conference on Information Technology: Research and Education (ITRE 2003), Newark, New Jersey, USA, pp. 243-250, Aug. 2003.
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"Adding 3D Graphics Support for PLX",
Proceedings of the IEEE International Conference on Information Technology: Research and Education (ITRE 2003), Newark, New Jersey, USA, pp. 40-44, Aug. 2003.
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"Architectural Enhancements for Fast Subword Permutations with Repetitions in Cryptographic Applications",
Proceedings of the International Conference on Computer Design (ICCD 2001), Austin, Texas, USA, pp. 453-461, Sept. 2001.
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B
"Blind De-anonymization Attacks using Social Networks",
Workshop on Privacy in the Electronic Society (WPES), Dallas, ACM, 30/10/2017.
Abstract
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"BitDeposit: Deterring Attacks and Abuses of Cloud Computing Services Through Economic Measures",
in Proceedings of the Workshop on Assured Cloud Computing (ACC), May 2013.
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"Butterfly and inverse Butterfly nets integration on Altera NioS-ii embedded processor",
44th IEEE Asilomar Conference on Signal, Systems and Computers, Pacific Grove, California, USA, November 2010.
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Bastion_rl,
, 2010 .
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"Bit Matrix Multiplication in Commodity Processors",
Proceedings of 19th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP ‘08), July 2008.
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"Bit Permutation Instructions for Accelerating Software Cryptography",
Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2000), Boston, Massachusetts, USA, pp. 138-148, July 2000.
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C
"CloudShelter: Protecting Virtual Machines’ Memory Resource Availability in Cloud Computing",
IEEE International Conference on Computer Design (ICCD), Boston, IEEE, 05/11/2017.
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"CATalyst: Defeating Last-Level Cache Side Channel Attacks in Cloud Computing",
Proceedings of IEEE Symposium on High Performance Computer Architecture (HPCA'16), Barcelona, Spain, March 2016.
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"Cloud Server Benchmark Suite for Evaluating New Hardware Architectures",
IEEE Computer Architecture Letters, July-Dec 2016.
Abstract
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"CloudRadar: A Real-time Side-channel Attack Detection System in Clouds",
Research in Attacks, Intrusion and Defense, September 2016.
Abstract
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"CloudMonatt: an Architecture for Security Health Monitoring and Attestation of Virtual Machines in Cloud Computing",
Proceedings of The 42nd International Symposium on Computer Architecture, Portland, pp. 362-274, June 2015.
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"Can randomized mapping secure instruction caches from side-channel attacks?",
in Proceedings of the Workshop on Hardware and Architectural Support for Security and Privacy (HASP), Portland, June 13, 2015.
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"Cyber Defenses for Physical Attacks and Insider Threats in Cloud",
Proceedings of the ACM Symposium on Information, Computer and Communications Security (AsiaCCS), June 2014.
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"Characterizing Hypervisor Vulnerabilities in Cloud Computing Servers",
in Proceedings of the Workshop on Security in Cloud Computing (SCC), May 2013.
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Checking Integrity of Untrusted Data with Few Queries,
, Princeton University Department of Electrical Engineering Technical Report CE-L2007-008, September 2007.
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"Covert and Side Channels due to Processor Architecture",
Proceedings of the 22nd Annual Computer Security Applications Conference (ACSAC'06), pp. 473-482, December 2006.
Abstract
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"Capacity Estimation of Non-Synchronous Covert Channels",
Proceedings of the 2nd International Workshop on Security in Distributed Computing Systems (SDCS 2005), Columbus, OH, USA, pp. 170-176, June 6-9, 2005.
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"Comparing Fast Implementations of Bit Permutation Instructions",
Proceedings of the 38th Annual Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, USA, pp. 1856-1863, Nov. 2004.
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"Cost-Effective Multiplication with Enhanced Adders for Multimedia Applications",
Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2000), vol. 1, Geneva Switzerland, pp. 651-654, May 2000.
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D
"Design, Implementation and Verification of Cloud Architecture for Monitoring a Virtual Machine’s Security Health",
IEEE Transactions on Computers, vol. 67, issue 6: IEEE, 06/2018.
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