Ruby B. Lee is the Forrest G. Hamrick Professor of Electrical Engineering at Princeton University. Her current research is in security-aware computer architecture, secure caches that do not leak information, secure cloud computing, secure virtual machines, smartphone security, running unvetted applications on sensitive data, and security verification. She has also done extensive past work on cryptographic acceleration, very fast and novel bit permutation instructions, secure processors and hardware trust anchors. Prior to Princeton, Lee served as chief architect at Hewlett-Packard for processor architecture, multimedia architecture, and then security architecture. She was a founding architect of HP’s PA-RISC architecture and instrumental in the initial design of several generations of PA-RISC processors for HP’s business and technical computers. She helped in the widespread adoption of multimedia in commodity products by pioneering multimedia support in microprocessors and introducing the first real-time software video in low-end products. She was co-leader of the Intel-HP multimedia architecture team for 64-bit microprocessors. She created the first security roadmap for enterprise and e-commerce security for HP. Lee is an ACM Fellow and IEEE Fellow, and holds over 120 U.S. and international patents. Known as a foremost hardware security expert, Lee is often asked to serve on national committees for improving cyber security research. Lee has a B.A. from Cornell and a Ph.D. from Stanford.
Robert C. Aitken is an ARM Fellow and heads the Silicon portion of ARM R&D. His areas of responsibility include low power design, library architecture for advanced process nodes, and resilient computing. His research interests include design for reliability, secure computing, and fault diagnosis. His group has participated in numerous chip tape-outs, including 6 at or below the 16nm node. He has published over 70 technical papers, on a wide range of topics. Dr. Aitken joined ARM as part of its acquisition of Artisan Components in 2004. Prior to Artisan, he worked at Agilent and HP. He has given tutorials and short courses on several subjects at conferences and universities worldwide. He holds a Ph.D. from McGill University in Canada. Dr. Aitken is an IEEE Fellow, and serves on a number of conference and workshop committees.
David Kaplan is a Principal Member of the Technical Staff at AMD working as a hardware (and sometimes software) security architect where he is responsible for architecting and ensuring security is a fundamental principle incorporated into AMD’s designs. His work includes the design of the AMD Platform Security Processor (PSP), cryptographic hardware, and various other security features for both general purpose and semi-custom hardware solutions. He is also actively involved in developing new and innovative security functionality for future AMD products. Prior to joining the security team in 2011, David worked for over 5 years on AMD low power CPU designs including the “Bobcat” and “Jaguar” cores. David has filed over 30 US patents and holds a B.S. degree from the University of Illinois at Urbana-Champaign.
Shay Gueron is a staff member of the Department of Mathematics at the University of Haifa. He is also a Senior Principal Engineer at Intel Corporation, at the Israel Development Center in Haifa, and is the Chief Core Cryptography Architect of the CPU Architecture Group.
Shay’s interests include applied cryptography, security, and algorithms. He has made multiple contributions to Intel’s architecture, micro architecture, security technologies, the design of algorithms and their efficient implementations in hardware and software. He was the lead technologist responsible to the addition of the AES-NI into Intel CPU’s, and also to introducing the carry-less multiplication instruction (PCLMULQD) for multiple usages, including acceleration of AES-GCM. He published papers on new algorithms for symmetric and public key cryptographic primitives. He also published open source software patches on algorithmic and software optimizations for RSA, ECC, SHA-256, SHA-512, AES in multiple modes, AES-GCM. For example, AES-GCM is today 25 times faster than its performance in 2009, before the hardware and software changes were introduced. With these, he helped drive continuous and significant speedups of important cryptographic algorithms, which are adopted in open source libraries such as OpenSSL and NSS. This has impact on reducing the cryptographic overhead for secure communications.